RISC-V: The New Kid on a Chip

RISC-V is a new instruction set architecture (ISA). To be extremely accurate, RISC-V is a family of ISAs, but it is common to refer to them as the RISC-V ISA. An ISA specifies the behaviors a given CPU manufacturer's processor implementation must exhibit in order to maintain binary compatibility with other implementations. To more easily reason and speak about ISAs, they are often given a classification. The seemingly most common classification being the architectural complexity, or more simply put, how many instructions are included in the specification. Using this form of classification, an ISA falls into one of two categories:

• Complex instruction set computers (CISC)
• Reduced instruction set computers (RISC)

There are a variety of different ISAs in existence. Well-known ISAs include x86 (CISC, commonly used by AMD and Intel), and arm (RISC, commonly used by Apple and Google).

RISC-V differentiates itself from many other ISAs through its modular design. The modularity of RISC-V's design allows for several base integer ISA variants and numerous optional extensions. The combination of these bases and extensions allow for implementations supporting embedded systems all the way up to supercomputer's with giant 128 bit address spaces.

The Big, Happy, RISC-V ISA Family (Aww! 👨‍👩‍👧‍👦)

From its name, it is obvious that the RISC-V ISA is classified as a RISC ISA. What may not be immediately obvious is that it's what's known as a load-store architecture. This means that the instructions fit into two categories:

• Memory access
• ALU operations

This means that the operands for a given instruction either both operate on registers, or they operate on memory. This is in contrast to many CISC ISAs (like x86) that are known as register-memory architectures, where any one operand of a given instruction may operate on memory or a register.

The RISC-V ISA defines several base integer (four, at the time of writing, to be exact) ISAs. The two primary ISAs are the 32-bit integer (RV32I) variant and the 64-bit integer (RV64I) variant. One of these base ISAs must be present in any valid implementation. It is important to note that the RV32I variant is not a strict super set of the RV64I variant. This decision was made consciously to allow implementors to make optimizations as needed to meet any memory or power constraints. This is also the reason that so many optional extensions exist. These extensions range from multiplication or floating-point arithmetic to compressed instructions to bit manipulation.

RISC-V CPU implementations that are meant to be suitable for general purpose computing generally implement the extensions I, M, A, F, D, Zicsr, Zifencei, and C. This set of extensions are so commonly implemented that they are denoted as RV32GC and RV64GC for 32 and 64 bits respectively.

There is one more member in the RISC-V family. The privileged ISA. This ISA covers "all aspects of RISC-V systems beyond the unprivileged ISA, including privileged instructions as well as additional functionality required for running operating systems and attaching external devices." The privileged ISA outlines the instructions needed to support operating systems and hypervisors, not just running applications on bare metal.

If you have any thoughts or questions about this post, feel free to start a discussion.

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